Class hours: Monday and Wednesday 14.15 - 16.00 in room H.204.
Office hours: Mondays 13:00 - 14:00 @ K319 (by appointment)
Instructor | Teaching Assistant(s) |
Vassilis Papaefstathiou | Mr. Sotiris Totomis |
Area: | Hardware and Computer Systems (E4) |
Description: | Performance metrics, pipelining and hazards, dynamic instruction scheduling with scoreboard and Tomasulo, ILP and static instruction scheduling, branch prediction, precise exceptions, speculation, multiple issue out-of-order superscalar processors, VLIW processors, thread level paralellism and multithreaded processors, multi-level cache memories and design optimizations, virtual memory and TLBs, multicore processors, snoop-based cache coherence, memory consistency, DRAM main memory technologies. |
ECTS: | 6 |
Prerequisites: | CS225 Computer Organization |
Grading: |
Homeworks/Assignments: 35% (grade must be > 4.5)
Midterm Exam: 20% (mandatory) Final Exam: 45% (grade must be > 4.5) |
Mailing-list: | hy425-list at csd dot uoc dot gr |
Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6th Edition/2020. Available in Greek (Klidarithmos Publishers, translation by D. Gizopoulos). ISBN 978-960-645-095-2.
William Stallings, Computer Organization and Architecture: Designing for Performance, 11th Edition/2020. Available in Greek (Tziolas Publishers, translation by M. Roumeliotis). ISBN 978-960-418-892-5.
Additional reading: Shen and Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, McGraw Hill, 2005, ISBN 0-07-059033-8.
Additional reading material will be posted as needed, during classes. Reading material includes Chapters from other textbooks (in English) and technical papers from conferences or journals covering the field of Computer Architecture.
Date | Description | Material | Reading List |
---|---|---|---|
Sep. 26 | Welcome and Introduction | ||
Sep. 28 | Introduction | Slides | Chapter 1 (1.1 - 1.4) from course textbook |
Oct. 03 | Metrics | Slides | Chapter 1 (1.5 - 1.13) from course textbook |
Oct. 05 | Metrics | Slides from Oct. 03 | |
Oct. 10 | Pipelining Review | Slides | Appendix C (C.1 - C.4) from course textbook |
Oct. 12 | Pipelining Review | Slides from Oct. 10 | |
Oct. 17 | Pipelining Review | Slides from Oct. 10 | |
Oct. 19 | Dynamic Instruction Scheduling: Scoreboard | Slides | Chapter 3 (3.1 - 3.2) & Appendix C (C.5 - C.10) from course textbook |
Oct. 24 | Dynamic Instruction Scheduling: Scoreboard | Slides from Oct. 19 | CDC 6600 original scoreboard design paper |
Oct. 26 | Dynamic Instruction Scheduling: Tomasulo | Slides | Chapter 3 (3.4) from course textbook |
Oct. 31 | Dynamic Instruction Scheduling: Tomasulo | Slides from Oct. 26 | Tomasulo's original paper |
Nov. 07 | Static Instruction Scheduling | Slides | |
Nov. 09 | Branch Prediction | Slides | |
Nov. 14 | Midterm Examination (mandatory 20%) | All lectures up to Static Instruction Scheduling (inclusive) | |
Nov. 16 | Branch Prediction | Slides from Nov. 09 |
1. Alternative implementations of two-level adaptive branch predictors
2. Combining branch predictors |
Nov. 21 | Reorder Buffer, Precise Exceptions and Speculation | Slides | |
Nov. 23 | Reorder Buffer, Precise Exceptions and Speculation | Slides from Nov. 21 | Implementing Precise Interrupts in Pipelined Processors (+ Future File) |
Nov. 28 | Multiple Issue Processors: Superscalar and VLIW | Slides | |
Nov. 30 | Prog. Assignment 1 + Solutions for Homework 1 & 2 (S. Totomis) | Programming Assignment 1 Homework 1 Homework 2 | |
Dec. 02 | Multiple Issue Processors: Superscalar and VLIW | Slides from Nov. 28 | Limits of Instruction-Level Parallelism |
Dec. 05 | Thread-Level Parallelism (TLP) | Slides | Sections 3.5, 3.6 |
Dec. 07 | Vector Processors | Slides | |
Dec. 09 | Cache memories: Design and performance analysis | Slides | |
Dec. 12 | Cache memories: Design and performance analysis | Slides from Dec. 09 | |
Dec. 14 | Cache design optimizations | Slides | |
Dec. 16 | Cache design optimizations | Slides from Dec. 14 |